compilation error on transformer stage
Posted: Wed Jan 04, 2012 9:40 am
whenever i use the transformer stage it gives compilation errors, remaining stages does n't gives erros
the transformer stage compilation error message is
##I TFCN 000001 00:04:46(000) <main_program>
Ascential DataStage(tm) Enterprise Edition 7.5
Copyright (c) 2004, 1997-2004 Ascential Software Corporation.
All Rights Reserved
##I TOSH 000002 00:04:46(001) <main_program> orchgeneral: loaded
##I TOSH 000002 00:04:46(002) <main_program> orchsort: loaded
##I TOSH 000002 00:04:46(003) <main_program> orchstats: loaded
##E TBLD 000000 00:04:47(000) <main_program> Error when checking composite operator: Subprocess command failed with exit status 256
##E TFSR 000019 00:04:47(001) <main_program> Could not check all operators because of previous error(s)
##W TFCP 000000 00:04:47(002) <transform> Error when checking composite operator: The number of reject datasets "0"is less than the number of input datasets "1".
##W TBLD 000000 00:04:47(003) <main_program> Error when checking composite operator: Output from subprocess: cxx: file 'C:/PROGRA~1/MKSTOO~1/etc/cxx.ccg': The system cannot find the file specified.
##I TFCP 000008 00:04:47(004) <transform> Error when checking composite operator: cxx -O -IC:/Ascential/DataStage/PXEngine/include -W/TP -W/EHa -DAPT_USE_ANSI_IOSTREAMS -c C:/Ascential/DataStage/Projects/indra/RT_BP1.O/V0S2_remdup_Transformer_2.C -o C:/Ascential/DataStage/Projects/indra/RT_BP1.O/V0S2_remdup_Transformer_2.tmp.o
##E TCOS 000029 00:04:47(005) <main_program> Creation of step finished with status = FAILED (remdup.Transformer_2)
*** Internal Generated Transformer Code follows:
0001: //
0002: // Generated file to implement the V0S2_remdup_Transformer_2 transform operator.
0003: //
0004:
0005: // define our input/output link names
0006: inputname 0 DSLink3;
0007: outputname 0 DSLink4;
0008:
0009: initialize {
0010: // define our row rejected variable
0011: int8 RowRejected0;
0012:
0013: // define our null set variable
0014: int8 NullSetVar0;
0015:
0016: // Stage variable declaration and initialisation
0017: int32 StageVar0_sv1;
0018: StageVar0_sv1 = 0;
0019: int32 StageVar0_sv2;
0020: StageVar0_sv2 = 0;
0021: }
0022:
0023: mainloop {
0024: // initialise our row rejected variable
0025: RowRejected0 = 1;
0026:
0027: // evaluate the stage variables first
0028: StageVar0_sv1 = StageVar0_sv2;
0029: StageVar0_sv2 = 0;
0030:
0031: // evaluate columns (no constraints) for link: DSLink4
0032: writerecord 0;
0033: RowRejected0 = 0;
0034: }
0035:
0036: finish {
0037: }
0038:
*** End of Internal Generated Transformer Code
the transformer stage compilation error message is
##I TFCN 000001 00:04:46(000) <main_program>
Ascential DataStage(tm) Enterprise Edition 7.5
Copyright (c) 2004, 1997-2004 Ascential Software Corporation.
All Rights Reserved
##I TOSH 000002 00:04:46(001) <main_program> orchgeneral: loaded
##I TOSH 000002 00:04:46(002) <main_program> orchsort: loaded
##I TOSH 000002 00:04:46(003) <main_program> orchstats: loaded
##E TBLD 000000 00:04:47(000) <main_program> Error when checking composite operator: Subprocess command failed with exit status 256
##E TFSR 000019 00:04:47(001) <main_program> Could not check all operators because of previous error(s)
##W TFCP 000000 00:04:47(002) <transform> Error when checking composite operator: The number of reject datasets "0"is less than the number of input datasets "1".
##W TBLD 000000 00:04:47(003) <main_program> Error when checking composite operator: Output from subprocess: cxx: file 'C:/PROGRA~1/MKSTOO~1/etc/cxx.ccg': The system cannot find the file specified.
##I TFCP 000008 00:04:47(004) <transform> Error when checking composite operator: cxx -O -IC:/Ascential/DataStage/PXEngine/include -W/TP -W/EHa -DAPT_USE_ANSI_IOSTREAMS -c C:/Ascential/DataStage/Projects/indra/RT_BP1.O/V0S2_remdup_Transformer_2.C -o C:/Ascential/DataStage/Projects/indra/RT_BP1.O/V0S2_remdup_Transformer_2.tmp.o
##E TCOS 000029 00:04:47(005) <main_program> Creation of step finished with status = FAILED (remdup.Transformer_2)
*** Internal Generated Transformer Code follows:
0001: //
0002: // Generated file to implement the V0S2_remdup_Transformer_2 transform operator.
0003: //
0004:
0005: // define our input/output link names
0006: inputname 0 DSLink3;
0007: outputname 0 DSLink4;
0008:
0009: initialize {
0010: // define our row rejected variable
0011: int8 RowRejected0;
0012:
0013: // define our null set variable
0014: int8 NullSetVar0;
0015:
0016: // Stage variable declaration and initialisation
0017: int32 StageVar0_sv1;
0018: StageVar0_sv1 = 0;
0019: int32 StageVar0_sv2;
0020: StageVar0_sv2 = 0;
0021: }
0022:
0023: mainloop {
0024: // initialise our row rejected variable
0025: RowRejected0 = 1;
0026:
0027: // evaluate the stage variables first
0028: StageVar0_sv1 = StageVar0_sv2;
0029: StageVar0_sv2 = 0;
0030:
0031: // evaluate columns (no constraints) for link: DSLink4
0032: writerecord 0;
0033: RowRejected0 = 0;
0034: }
0035:
0036: finish {
0037: }
0038:
*** End of Internal Generated Transformer Code