bulidops stages

[murari83]

hi all,

I am writing userdefine stages.its shwoing this error.



seq------>bulid-------------->seq


code is like this


if(b==0 || indata.b<mindiv){

transferAndWriteRecord(1);

//rej.a=indata.a;
//rej.b=indata.b;
//writeRecord(1);

}else{

doTransfer(0);

q=indata.a;
div=indata.b;

res=indata.a/indata.b;
rem=(indata.a)%(indata.b);

writeRecord(0);
}


i am getting this error

Operator Generation Failed

buildop -f -BC /usr/vacpp/bin/xlC_r -BL /usr/vacpp/bin/xlC_r -C buildop -H buildop -O buildop -W buildop buildop/divide.opd

##E TCBO 000000 APT_BUILDOP_Operator: schema variables are not permitted when transfers are specified explicitly.

plese give me the suggestion.


Thanks

[ag_ram]

##E TCBO 000000 APT_BUILDOP_Operator: schema variables are not permitted when transfers are specified explicitly.

This does sound that you have defined tranfers while defining this Build Op stage but you use the output schema explicitly.

Each transfer says that OUTput schema shoud be derived by Which INput schema. Moreover, You can assign multiple INput schemas to a single OUTput schema resulting accumulation of all INput schemas in the OUTput schema.

Check whether transfer is defined anyway and Remove transfer for which you are defining the output schema inside the code.